![]() PC_next assign pc_next = (JRControl = 1'b1) ? PC_jr : PC_4beqj ĭata_memory datamem(.clk(clk).mem_access_addr(ALU_out), PC_4beqj assign PC_4beqj = (jump = 1'b1) ? PC_j : PC_4beq jump shift left 1 assign jump_shift_1 = Instr_mem instrucion_memory(.pc(pc_current).instruction(instr)) PC always posedge clk or posedge reset)Įnd // PC + 2 assign pc2 = pc_current + 16 'd2 Wire signed im_shift_1, PC_j, PC_beq, PC_4beq,PC_4beqj,PC_jr Wire sign_ext_im,read_data2,zero_ext_im,imm_ext Wire jump,branch,mem_read,mem_write,alu_src,reg_write : FPGA projects, Verilog projects, VHDL projects // Verilog project: Verilog code for 16-bit MIPS Processor // Verilog code for 16 bit single cycle MIPS CPU module mips_16( input clk,reset, Output reg jump,branch,mem_read,mem_write,alu_src,reg_write,sign_or_zeroĮnd endcase end end endmodule Verilog code for the single-cycle MIPS processor: : FPGA projects, Verilog projects, VHDL projects // Verilog project: Verilog code for 16-bit MIPS Processor // Submodule: Control Unit in Verilog module control( input opcode,
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